1. Field of the Invention
The present invention relates to a method of producing a semiconductor device, such as an integrated circuit (IC) of bipolar transistors or metal oxide semiconductor (MOS) transistors.
2. Description of the Prior Art
In order to improve the performance of semiconductor devices and to increase their density, persons skilled in the art have been reducing the dimensions of the component elements. For example, they are narrowing the base width of bipolar transistors and shortening the channel length of MOS transistors so as to increase the gain and decrease the parasitic capacitance, thereby resulting in increased operating speeds. One method of reducing the dimensions of elements is the fine processing technique wherein fine patterns of, for example a resist film, insulating film, conductive film, etc., are formed for miniaturization. Along with this fine processing technique, attempts have been made to self-align fine patterns with previous fine patterns. In production of a bipolar semiconductor device, it has been proposed to form active regions of a bipolar transistor by a self-alignment system using a mask (for example, cf. Proc. of 12th Conf. on Solid State Devices, Tokyo, Aug. 1980, pp. 67-68 (abstract from Tetsushi Sasaki et al., "HIGH SPEED BIPOLAR IC'S USING SUPER SELF-ALIGNED PROCESS TECHNOLOGY", Proc. of 12th Conf. on Solid-State Devices, Japanese Journal of Applied Physics, Vol. 20, ( 1981), Supplement 20-1, pps. 155-159), and Japanese Unexamined Patent Publication (Kokai) No. 57-178364). This technique, however, involves a relatively large number of complex production steps and makes it difficult to obtain sufficient control of dimensions. In the production of an MOS semiconductor device, a source region and a drain region have been self-aligned by using a polycrystalline silicon gate. No other means of self-alignment of the source and drain regions, however, has yet been practiced.